The present invention relates to an output buffer circuit for semiconductor integrated circuits, and an output buffer enabling an input/output interface between semiconductor integrated circuits operated by different power voltages.
As the degree of integration of the semiconductor integrated circuits has been on the increase and high speed performances have also been improved, the required power has also been increased. In order to reduce the power voltage level, it is possible that two or more semiconductor integrated circuits are provided in a single wafer, wherein the semiconductor integrated circuits axe driven or operated by different power voltage levels. It is here assumed that the first semiconductor integrated circuit is operated or driven by the low power voltage, whilst the second semiconductor integrated circuit is operated or driven by the high power voltage. If the first and second semiconductor integrated circuits are directly connected to each other, then a leakage of current at a few milliamperes may flow through an input buffer circuit of the second semiconductor integrated circuit during when signals transmitted between the first and second semiconductor integrated circuit are in the high level. This problem is serious particularly with large scale integrated circuits including high power voltage semiconductor integrated circuits, each of which has more than several tend to input terminals through which leakage of currents flow, resulting in a remarkable increase in power consumption.
In Japanese laid-open patent publication No. 4-243321, it is disclosed to settle the above problem with the increased power consumption, wherein an output buffer circuit as an interface circuit is disposed between first and second semiconductor integrated circuits driven by different power voltage levels.
In Japanese laid-open patent publication No. 6-291638, it is disclosed to reduce a leakage of current flowing through a direct connection between the low power voltage semiconductor integrated circuit and the high power voltage semiconductor integrated circuit.
The conventional interface circuit is disposed between the first and second semiconductor integrated circuits driven by the low and high power voltages respectively. This conventional interface circuit comprises an output buffer circuit and an n-channel depletion MOS field effect transistor connected in series between an output node of the output buffer and an input/output pad of the second semiconductor integrated circuit driven by the high power voltage level. The n-channel depletion MOS field effect transistor is formed in a p-well region. The output buffer circuit comprises a complementary MOS circuit which comprises a series connection of n-channel and p-channel enhancement type MOS field effect transistors. If a low voltage signal level is outputted from the input/output pad, then the output node side source electrode of the n-channel depletion MOS field effect transistor becomes the ground level so that the output node side source electrode of the n-channel depletion MOS field effect transistor becomes equal to the voltage of the p-well in which the n-channel depletion MOS field effect transistor is formed. If a high voltage signal level is outputted from the input/output pad, then the p-channel enhancement MOS field effect transistor turns ON so that the output node side source electrode of the n-channel depletion MOS field effect transistor becomes the high level or the power voltage level. However the voltage of the p-well region, in which the n-channel depletion MOS field effect transistor is formed, is fixed at the lowest voltage level or the ground level, for which reason the p-well region is applied with a back bias, whereby a threshold voltage of the depletion type n-channel MOS field effect transistor is raised, resulting in a remarkable deterioration in driving capability of the depletion type n-channel MOS field effect transistor.
In order to solve the above problem with the remarkable deterioration in driving capability of the depletion type n-channel MOS field effect transistor when the high voltage level is outputted from the input/output pad 5, it was proposed to increase the gate width of the depletion type n-channel MOS field effect transistor to attempt to increase the current driving capability. Since, however, the current driving capability depends upon the series connection of the driver transistor in the buffer circuit and the depletion type n-channel MOS field effect transistor, variations in the current driving capability are as illustrated in FIG. 1. If the driving capability of the depletion type n-channel MOS field effect transistor becomes much larger than the driving capability of the driver transistor in the buffer circuit, then the current driving capability is influenced mainly by the characteristic Or the driving capability of the driver transistor of the buffer circuit. For this reason, even if the gate width of the depletion type n-channel MOS field effect transistor is remarkably increased thereby the layout area thereof is also remarkably increased, a small increase in driving capability is obtained. This means that the degree of the integration of the circuits is deteriorated. Also even if the driving capability of the driver transistor in the buffer circuit becomes much larger than the depletion type n-channel MOS field effect transistor, then the current driving capability is influenced mainly by the characteristic or the driving capability of the depletion type n-channel MOS field effect transistor. For this reason, even if the gate width of the driver transistor in the buffer circuit is remarkably increased thereby the layout area thereof is also remarkably increased, a small increase in driving capability is obtained. This means that the degree of the integration of the circuits is deteriorated.
In the above circumstances, it had been required to optimize a driving capability of a depletion type MOS field effect transistor provided between an output node of a buffer circuit connected with the low power voltage semiconductor integrated circuit and an input/output pad of the high power voltage semiconductor integrated circuit.